(1) Field of the Invention
The present invention relates to a communication node apparatus, and more specifically to a communication node apparatus for performing routing processing on packets received from input lines at high speed.
(2) Description of the Related Art
A communication node apparatus for interconnecting a plurality of networks with each other needs to perform routing processing on received packets from respective input lines at high speed. Of the communication node apparatus, routers for routing variable length packets typified by IP (Internet Protocol) packets, for example, have a plurality of line interfaces connected to input/output lines, respectively. As basic control functions, each router has a route calculating function for calculating communication pass information (hereinafter called xe2x80x9crouting informationxe2x80x9d) for respective networks, based on a predetermined routing protocol and storing the result of calculation in a memory (hereinafter called xe2x80x9crouting tablexe2x80x9d), and a routing processing (route reference) function for referring to the routing table, based on a destination address of each received packet and transferring or forwarding each received packet to a route specified by the routing information.
In the conventional routers, the route calculating function and the routing processing function have been implemented by one control processor. However, various proposals for improving a processing speed at a router controller have been made with an increase in the scale of each network, the speeding-up of a transmission rate or an increase in data traffic due to the diversification of communication applications.
As one means for speeding up routing processing, there has been proposed a router structure wherein a route calculating function and a routing processing function are separated from each other, which is entitled xe2x80x9cTrend: Target on Gygabit/Router Internet Highway Following One Anotherxe2x80x9d, p.p. 124-127, the Nov. 3, 1997 of Nikkei Communication (Nikkei BP Co., Ltd.), for example (prior art 1). The above-described reference discloses a router structure wherein processors for routing processing and routing tables are provided every line interface boards and respective routing information calculated by a route calculating processor are distributed to the respective line interface boards, thereby to reduce the load on the route calculating processor and to perform the routing of received packets within the respective line interface boards at high speed. Further, the above-described reference also discloses a router structure wherein the routing processing for each line interface board is implemented by an ASIC (Application Specific Integrated Circuit) which is an IC intended for specific uses or applications.
Japanese Published Unexamined Patent Application No. Hei 7-177172 (prior art 2) has proposed a router which comprises a whole control unit provided with a routing table serving as an original and a route calculating function, a plurality of relay processing units respectively connected to a plurality of input/output lines and having individual routing tables, and wherein when the whole control unit calculates new routing information, the routing information is registered in the original routing table and notified to each relay processing unit via a system bus, so that the respective relay processing units update their individual routing tables.
Japanese Published Unexamined Patent Application No. Hei 9-275413 (prior art 3) has proposed a router which comprises a master module for performing route calculations and a plurality of link modules respectively connected to input/output lines, each of said link modules having a cache memory for storing therein the required minimum of routing information notified from the master module. When information necessary for routing a received packet does not exist in the cache memory, the received packet is transferred to the master module, so that the master module performs the routing on the received packet.
According to the xe2x80x9cATM and IP Integrated Switch Architecturexe2x80x9d published in the collection of theses at Communication Society of 1998 of The Institute of Electronics, Information and Communication Engineers, pp.598-599, SB-7-3 (prior art 4), there has been proposed an architecture of an ATM/IP integrated switch wherein an ATM (Asynchronous Transfer Mode) switch and a router are integrated with each other so that IP packets arrived in a form of cells are subjected to IP layer processing as cells as they are. In the above-described switch, each of said line cards (line interface boards) is provided with a cache memory for a routing table, and a processor card having a route calculating function performs transfer processing on a specific packet for which any one of said line cards has failed to resolve the destination. Then the cache memory is immediately brought up to date so that the subsequent packets having the same destination address can be transferred on the respective line cards.
According to the routing system, in which routing tables for storing all the routing information are placed in the respective line interface boards as the prior arts 1 and 2, the routing for the received packets can be advantageously performed on the respective line interface boards at high speed, but it needs numbers of memories each having large capacity.
On the other hand, according to the routing system, in which cache memories each having relatively small capacity are placed in the respective line interface boards as the prior arts 3 and 4, it needs to download a new routing information entry to the line interface from the route calculation unit storing all the routing information when routing information necessary for a received packet is not found in the cache memory.
If the storage capacity of the cache memory is filled up in this case, it is necessary to delete any of the already registered routing information entries in order to accept the new routing information entry. However, the prior arts do not provide a beneficial proposal about the deletion of the routing information from the cache memory. Accordingly, a problem arises in that downloading requests on the same routing information deleted once from the cache memory are issued repeatedly and the unreasonable update processing of the cache memory delays the speed of the routing processing.
It is an object of the present invention to provide a communication node apparatus capable of deleting unnecessary routing information from a cache memory on each line interface board with suitable timing.
It is another object of the present invention to provide a communication node apparatus capable of registering new routing information while avoiding a repetition of unreasonable updating processing of a cache memory to the utmost when the cache memory on each line interface board is filled up.
In order to achieve the above objects, a communication node apparatus according to the present invention comprises a route management unit having a main routing table for storing therein a plurality of routing information entries necessary for communication node, and a plurality of line interfaces equipped to every input and output lines, wherein each of said line interfaces includes a sub routing table for storing therein a limited number of routing information entries loaded from the route management unit, a received packet processing circuit for performing routing processing on a packet received from one of said input lines by referring to the sub routing table, and a table management unit for eliminating a specific routing information entry already registered in the sub routing table, based on predetermined information extracted from said packet received from said input line.
The table management unit checks, for example, a control information field defined in a predetermined position of each of said packets received from the input line and deletes a specific routing information entry, which corresponds to a specific packet having first control information contained in the control information field, from the sub routing table.
Another feature of the present invention resides in that the table management unit includes registering means for requesting the route management unit to download a non-registered routing information entry corresponding to the packet received from the input line and registering a new routing information entry downloaded from the route management unit in the sub routing table.
A further feature of the present invention resides in that the registering means checks a control information field defined in a predetermined position of the packet received from the input line, and registering a routing information entry downloaded in association with a specific packet which includes second control information in said control information field, into said sub routing table together with a high priority indication. According to the priority indication, the registering means can sacrifice any free of the high priority indication, of the routing information entries already registered in the sub routing table, in order to register the new routing information entry into the sub routing table when no idle area exists in a sub routing table.
While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings.